Microelectronics products are generally classified into two categories: logic devices and memory devices. As an important type of memory devices, Dynamic Random Access Memories (DRAMs) can support high-speed reading/writing of data. However, stored data will easily get lost in case of power-off. Therefore, the DRAMs are called volatile semiconductor memories. In a computer system, the DRAM has a data processing speed lower than that of a high-speed microprocessor and higher than that of a low-speed non-volatile memory, and thus achieves matching between high-speed data processing and low-speed data accessing. With continuous development of the information technology, high-speed and high-density DRAMs become an important trend of the current memory researches.
A conventional DRAM cell comprises an access transistor and a capacitor (1T1C). The capacitor is configured to store data, and the transistor is configured to control reading/writing of the data. With scaling-down of the memory cell, it has become difficult for the conventional 1T1C structure to satisfy requirements such as low leakage current of the transistor and large storage capability of the capacitor. Meanwhile, for either a trench-type capacitor or a stack-type capacitor, it is difficult to reduce the size thereof while ensuring a capacitance larger than 25 pF. Therefore, the current memory researches focus on seeking a new DRAM cell structure.
Currently, Floating-Body memory Cells (FBCs) are attracting attentions from the industry due to its complete compatibility with conventional processes and flexibility of switching. FIG. 1A is a schematic view showing an existing FBC implemented on an SOI substrate. FIG. 1B is a schematic view showing an existing FBC cell implemented on a bulk-silicon substrate. As shown in FIG. 1A and FIG. 1B, the memory cell comprises: an electrode formed as a back-gate electrode under a back-gate insulation layer (FIG. 1A) or an N-type heavily-doped region (FIG. 1B); a channel region on the substrate; a gate region above the channel region; and a source region and a drain region on the substrate and at opposite sides of the channel region.
FIG. 2 is a schematic view illustrating the data storage principle of an existing FBC cell. As shown in FIG. 2, when the device is being programmed, a high positive voltage Vd is applied to the drain region, and an on-voltage Vg of the transistor is applied to the gate, wherein Vg=Vd/4˜Vd/2. In such a case, electrons obtain high energy during its movement from the source region to the drain region, and thus cause impact ionization under a high electrical field near the drain region to generate electron-hole pairs. The holes move toward the substrate. Because silicon dioxide (in case of the SOI substrate) or N-type heavily doped bulk-silicon creates a barrier on the path of the holes moving toward the substrate, the holes accumulate near the substrate. The accumulation of the holes raises the potential of the substrate and therefore reduces the threshold voltage of the transistor. This state is referred to as a write state (“1” state). If a negative voltage is applied to the source region or the drain region, the holes stored near the substrate will be removed, raising the threshold voltage of the transistor. This state is referred to as an erase state (“0” state). A combination of the “0” state and the “1” state will achieve a high-speed erasing/writing operation. Unlike the conventional 1T1C structure, the FBC cell structure avoids process complexity due to the complex capacitor structure, and meanwhile can achieve high-density integration of the memory cells.
Though the FBC cell structure has many advantages in terms of process complexity and high-density integration, it still faces some challenges in connection with data holding duration. The existing technology has a disadvantage that if the FBC cell is not in a programmed state, the holes stored near the substrate tend to leak through a PN junction between the source region and the substrate, or a PN junction between the drain region and the substrate. As a result, the data holding duration of the FBC cell is short, which may be less than 1 second. Accordingly, the memory device has an increased number of refreshing operations and also increased power consumption.